`timescale 1ns/1ns
`define k 256
`define m 16

module CSA(input [`k+`m+2:0] a,
		   input [`k+`m+2:0] b,
		   input [`k+`m+2:0] d,
		   output [`k+`m+2:0] c,
		   output [`k+`m+2:0] s);
		   
assign s = a ^ b ^ d;
assign c = ((a & b) | (a & d) | (b & d));

endmodule